The VPX570 provides an ADC supporting rates up to 5.4 GSPS and a DAC supporting rates up to 6 GSPS, both at 12 bits. The EV12DS460A and EV12AS350A both provide parallel interfaces to the FPGA, avoiding latency associated with serializing/deserializing data. The XCVU13P FPGA has large 360 Mb on-chip UltraRAM which, with the ADC and DAC selection, allows this module ideal for low-latency applications such as DRFM, radar simulators and smart jammers.
 
The FPGA interfaces directly to rear I/O via SERDES and LVDS, supporting PCIe, SRIO, GbE/10GbE/40GbE or Aurora backplane connections. General purpose I/O signals, e.g. for trigger, are routed to the front panel that also contains 8 LED/Bi-color.
 
ADC and DAC have a average sampling clock, which can be fed from front panel (Direct RF Clock) or from PLL locked to a 10/100 MHz reference clock sourced from front panel or backplane. Sampling clock selection is by ordering option.
 
The VPX570 includes platform health management/monitoring capability using VadaTech’s field-proven IPMI software. An on-board management controller has the ability to access board sensors and manage FPGA image updates.
 
The unit is available in a range of temperature and shock/vib specifications per ANSI/VITA 47, up to V3 and OS2.


This article is originally posted on Tronserve.com